A High-Level Modeling System (HLMS) refers to a computer-based circuit design tool that allows circuit designers to create circuits at a high level of abstraction. Typically, an HLMS provides a graphic design environment within which circuit designers create circuit designs using a “drag-and-drop” design paradigm. A circuit designer can drag graphic blocks into the design environment. Each graphic block represents a particular circuit function. For example, each graphic block can represent a function such as multiplexing, addition, multiplication, filtering, or the like. Within the design environment, the circuit designer also can specify connectivity and signal flows among the graphic blocks by drawing lines that interconnect the various blocks.
One example of an HLMS is Xilinx System Generator for Digital Signal Processing (DSP), also known as “SysGen.” SysGen is a high-performance, computer-based design tool that executes as part of Simulink to provide a high-level, graphical modeling environment. Simulink runs in Matlab from The MathWorks, Inc., of Natick, Mass. and is an interactive tool for modeling, simulating, and analyzing dynamical systems.
Circuit designers are permitted to add comments to a circuit design within the HLMS design environment. The comments provide descriptive information relating to the various parts of the HLMS circuit design. At some point in the development process, the HLMS circuit design is transformed into hardware description language for further processing and ultimately implementation within an IC. The resulting HDL is devoid of commentary and other information from the HLMS circuit design. As such, attempting to correlate different portions of HDL to the blocks of the HLMS circuit design can be difficult. The lack of explanatory information also complicates further design efforts directed to the HDL itself.